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1 m e m o r y all data sheets are subject to change without notice (858) 503-3300- fax: (858) 503-3301- www.maxwell.com 14-bit, 10 msps monolithic a/d 9240lp ?2005 maxwell technologies all rights reserved. 01.10.05 rev 6 converter with lpt asic f eatures : ?r ad -p ak ? radiation-hardened against natural space radiation low power dissipation: 295 mw single 5 v supply integral nonlinearity error: 2.5 lsb differential nonlinearity error: 0.6 lsb input referred noise: 0.36 lsb complete: on-chip sample-and-hold amplifier and voltage reference signal-to-noise and distortion ration: 77.5 db spurious-free dynamic range: 90 db out-of-range indicator straight binary output data total dose hardened to 100 krads (si), dependent on orbit and mission duration single event latchup (sel) protected d escription : maxwell technologies? 9240lp is a 14-bit, analog-to-digital converter that operates at a 10 msps rate. manufactured with a high speed cmos process, this adc contains an on-chip, high performance, low noise, sample-and-hold amplifier and programmable voltage reference. the 9240lp offers single supply operation and dissipates only 295 mw with a 5 volt supply. this device provides no missing codes and excellent temperature drift performance over the full operating temperature range. the 9240lp utilizes maxwell?s lpt? latchup protection circuit. maxwell technologies' patented r ad -p ak ? packaging technology incorporates radiation shielding in the microcircuit package. it eliminates the need for box shielding while provid- ing the required radiation shielding for a lifetime in orbit or space mission. in a geo orbit, r ad -p ak ? provides protection to 100 krad (si) radiation dose tolerance. this product is avail- able with screening up to maxwell technologies self-defined class k. bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 5 bit 3 nc bias capb capt nc cml lptref vina vinb lptdvdd lptavdd dvss avss dvdd avdd nc drvdd clk lptstatus lptbit nc bit 14 refcom vref sense nc avss avdd nc nc otc bit 1 bit 2 9240lp 9240lp b lock d iagram dvdd drvdd vina vinb vref lptvref lptbit avdd lptavdd lptdvdd lptdrvdd lptvina lptvinb lptvref lptstatus crow bar avdd dvdd drvdd vina vinb vref current sense 9240 14 bit a/d data outputs control signals
m e m o r y 2 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp t able 1. 9240lp p in d escription p in n umber n ame d escription 1 dvss digital ground 2, 29 avss analog ground 3 dvdd 5v digital supply 4, 28 avdd 5v analog supply 5 nc no connect 6 drvdd digital output driver supply 7 clk clock input pin 8 lptstatus a 0 to 5v square-wave is output during the deci- sion time and protect time. normally low. 9 lptbit the lpt circuit will crowbar the power supplies to the 9240 for as long as a logic high is applied. used to verify operation of the lpt. normally a logical low or ground is applied to this input. 10 nc no connect 11 bit 14 least significant data bit (lsb) 12-23 bit 13-bit 2 data output bits 24 bit 1 most significant data bits (msb) 25 otr out of range 26, 27, 30 nc no connect 31 sense reference select 32 vref reference i/o 33 refcom reference common 34, 38 nc no connect 35 bias 1 1. see speed/power programmability section. power/speed programming 36 capb noise reduction pin 37 capt noise reduction pin 39 cml common-mod level (midsupply) 40 lptvref protected reference i/o 41 vina analog input pin (+) 42 vinb analog input pin (-) 43 lptdvdd protected 5v digital supply 44 lptavdd protected 5v analog supply
m e m o r y 3 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp t able 2. 9240lp a bsolute m aximum r atings 1 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification are not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. p arameter s ymbol w ith r espect t o m in t yp m ax u nit avdd avss -0.3 6.5 v dvdd dvss -0.3 6.5 v avss dvss -0.3 0.3 v avdd dvdd -6.5 6.5 v drvdd drvss -0.3 6.5 v drvss avss -0.3 0.3 v refcom avss -0.3 0.3 v clk avss +0.3 avdd -0.5 v digital outputs drvss -0.3 drvdd + 0.3 v vina, vinb avss -0.3 avdd + 0.3 v vref avss -0.3 avdd + 0.3 v sense avss -0.3 avdd + 0.3 v capb, capt avss -0.3 avdd + 0.3 v bias avss -0.3 avdd + -.3 v junction temperature t j -- 150 c operating temperature t a -55 125 c package weight -- 10.5 -- grams thermal resistance t jc -- 9.6 -- c/w storage temperature t stg -65 150 c lead temperature (10 sec) t l -- 300 c
m e m o r y 4 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp t able 3. 9240lp dc s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k ? , v ref = 2.5v, v in a=v in b = 2.5v d ifferential i nput c entered on v ref (1.25v to 3.75v a bsolute ) t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp 1 m ax u nit resolution 1 14 -- -- bits min max conversion rate 9, 10, 11 10 -- -- mhz min max referred noise 1 v ref = 1 v v ref = 2.5v -- -- 0.9 0.36 -- -- lsb rms accuracy 2 integral nonlinearity (inl) differential nonlinearity (dnl) inl 3 dnl 3 no missing codes zero error (@ 25 c) gain error (@ 25 c) 1,4 gain error (@ 25 c) 5 1, 2, 3 1, 2, 3 1 1 1 -3 -1 -- -- -- -- -- -- 2.5 0.6 2.5 0.7 -- -- -- -- 3 1.0 -- 14 0.3 1.5 0.75 lsb lsb lsb lsb bits guaranteed % fsr % fsr % fsr temperature drift zero error gain error 4 gain error 5 1, 2, 3 -- -- -- 3.0 20.0 5.0 -- -- -- ppm/c ppm/c ppm/c power supply rejection 1, 2, 3 -- -- 0.1 % fsr analog input 1 input span (with v ref = 1.0 v) (with v ref = 2.5 v) input (v in a or v in b) range input capacitance 1, 2, 3 2 -- 0 -- -- -- -- 16 -- 5 avdd -.25 -- v p-p v p-p v pf internal voltage reference 1 output voltage (1v mode) output voltage tolerance (1 v mode) output voltage (2.5 v mode) output voltage tolerance (2.5 v mode) load regulation v ref load regulation lptv ref 6,7 -- -- -- -- -- -- 1 -- 2.5 -- 10 -- -- 14 -- 35 -- 10.0 v mv v mv mv mv reference input resistance 1, 2, 3 -- 5 -- k ?
m e m o r y 5 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp lpt asic rds on - v ref - avdd - dvdd - v in a - v in b latchup protection - decision time - protect time - avdd trip current - avdd trip current tolerance - dvdd trip current - dvdd trip current tolerance 1, 2, 3 8 8 105 105 10 70 75 15 28 5 15 ? ? ? ? s s ma ma ma power supplies supply voltages - avdd - dvdd - drvdd supply current - iavdd - idvdd 1, 2, 3 1, 2, 3 -- -- -- -- -- 5 5 5 43 3 5 5 5 55 16 v (5% avdd operating) v (5% dvdd operat- ing) v (5% drvdd operat- ing) ma ma power consumption 8 295 355 mw 1. guaranteed by design 2. tested using external v ref with servo control 3. v ref = 1v 4. including internal reference 5. excluding internal reference 6. load regulkation with 1 ma load current 7. lptv ref should not be capacitively loaded above 0.1uf 8. calculated from i dd t able 3. 9240lp dc s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k ? , v ref = 2.5v, v in a=v in b = 2.5v d ifferential i nput c entered on v ref (1.25v to 3.75v a bsolute ) t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp 1 m ax u nit
m e m o r y 6 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp t able 4. 9240lp ac s pecifications (avdd = 5v, dvdd = 5v, drvdd = 5v, f sample = 10msps, bias = 2 k ? , v ref = 2.5v, v in a = -0.5dbfs, ac c oupled /d ifferential i nput , t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups m in t yp 1 1. guaranteed by design m ax u nit signal-to-noise and distortion ratio (s/n+d) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz -- -- -- 76.0 76.0 75.5 -- -- -- db db db effective number of bits (enob) 2 f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 2. enob calculated from snr 12 -- -- -- 12.3 11.9 -- -- -- bits bits bits signal-to-noise ration (snr) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 4, 5, 6 74.5 -- -- 77 77 77 -- -- -- db db db total harmonic distortion (thd) f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz -- -- -- -76.0 -83.0 -75.0 -- -- -- db db db spurious free dynamic range f input = 500 khz f input = 1.0 mhz f input = 5.0 mhz 4, 5, 6 -- -- -- 90.0 90.0 80.0 -- -- -- db db db dynamic performance 1 full power bandwidth small signal bandwidth aperture delay aperture jitter acquisition to full-scale step (0.0025%) overvoltage recovery time -- -- -- -- -- -- 70 70 1 4 45 167 -- -- -- -- -- -- mhz mhz ns ps rms ns ns t able 5. 9240lp d igital s pecifications (avdd = 5v, dvdd = 5v, t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups s ymbol m in t yp m ax u nit clock input 1 high level input voltage 2 low level input voltage high level input current (v in = dvdd) low level input current (v in = 0v) input capacitance 1, 2, 3 v ih v il i ih i il c in 3.5 -- -- -- -- 5 -- 1.0 10 10 -- v v a a pf
m e m o r y 7 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp logic outputs (with drvdd = 5v) high level output voltage (i oh = 50 a) high level output voltage (i oh = 0.5 ma) low level output voltage (i ol = 1.6 ma) low level output voltage (i ol = 50 a) output capacitance 1, 2, 3 v oh v oh v ol v ol c out 5 4.5 2.4 0.4 0.1 -- v min v min v max v max pf typ 1. due to the voltage drop across the lpt circuiry the clock signal must be no greater than avdd - 0.5v 2. guaranteed by design t able 6. 9240lp s witching c haracteristics 1 (t a = -55 to +125c with avdd = 5v, dvdd = 5v, drvdd = 5v, r bias = 2 k w, c l = 20 p f) 1. guaranteed by design p arameter s ymbol m in t yp m ax u nits clock period clock pulse width high clock pulse width low output delay pipeline delay (latency) t c t ch t cl t od 100 45 45 8 -- -- -- -- 13 -- -- -- -- 19 --3 ns ns ns ns clock cycles t able 5. 9240lp d igital s pecifications (avdd = 5v, dvdd = 5v, t a = -55 to +125c, unless otherwise specified ) p arameter s ubgroups s ymbol m in t yp m ax u nit
m e m o r y 8 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp t ypical d ifferential c haracterization c urves /p lots (avdd = 5v, dvdd = 5v, drvdd = 5v, f sample = 10 msps, r bias = 2 k w, t a = 25 c, d ifferential i nput ) f igure 1. t iming d iagram clk avdd dvdd drvdd bias cml otr 14 b it o utput dvss avss refcom drvss v in a v in b lptref capa capt vref s ense lptavd ref 5v 0.1 uf 0.1 uf 10 uf 10k 2k 0.1 uf m ode s elect o utput d rivers d igital c orrection l ogic 4 44 4 14 a/d a/d a/d a/d mdac 1 mdac 2 mdac 3 r ecommended e xternal r eference
m e m o r y 9 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 2. sinad vs . i nput f requency (i nput s pace = 2v, vcm = 2.5v) f igure 3. thd vs . i nput f requency (i nput s pan = 5v, vcm = 2.5v)
m e m o r y 10 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 4. t ypical fft, f in = 1.0 mh z (i nput s pace = 5v, v cm = 2.5v) f igure 5. sinad vs . i nput f requency (i nput s pan = 2v, vcm = 2.5v) f igure 6. thd vs . i nput f requency (i nput s pan = 2v, v cm = 2.5v)
m e m o r y 11 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 7. t ypical fft, f in = 5.0 mh z (i nput s pan = 2 v, v cm = 2.5 v) f igure 8. thd vs . s ample r ate (f in = 5.0 mh z , a in = -0.5 d bfs, v cm = 2.5 v) f igure 9. s ingle t one sfdr (f in = 5.0 mh z , v cm = 2.5 v)
m e m o r y 12 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 10. d ual t one sfdr ( f 1 = 0.95 mh z , f 2 = 1.04 mh z , v cm = 2.5 v) f igure 11. t ypical inl (i nput s pan = 5 v) f igure 12. t ypical dnl (i nput s pan = 5 v)
m e m o r y 13 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 13. ?g rounded -i nput ? h istogram (i nput s pan = 5 v) f igure 14. sinad vs . i nput f requency (i nput s pan = 2 v, v cm = 2.5v)
m e m o r y 14 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 15. thd vs . i nput f requency (i nput s pan = 5 v, v cm = 2.5 v) f igure 16. cmr vs . i nput f requency (i nput s pan = 2 v, vcm = 2.5 v)
m e m o r y 15 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 17. sinad vs . i nput f requency (i nput s pan = 5 v, v cm = 2.5 v) f igure 18. thd vs . i nput f requency (i nput s pan = 5 v, v cm = 2.5 v)
m e m o r y 16 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp f igure 19. t ypical v oltage r eference e rror vs . t emperature 44 p in r ad -p ak ? q uad f lat p ackage s ymbol d imension m in n om m ax a 0.185 0.205 0.225 b 0.015 0.017 0.019 c 0.008 0.010 0.012 d 0.643 0.650 0.657
m e m o r y 17 01.10.05 rev 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 14-bit, 10 msps monolithic a/d converter with lpt asic 9240lp note: all dimensions in inches important notice: these data sheets are created using the chip manufacturers published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts. d1 0.500 bsc e 0.050 bsc s1 0.005 0.067 -- l 0.260 0.270 0.280 q 0.020 0.025 0.030 n44 44 p in r ad -p ak ? q uad f lat p ackage s ymbol d imension m in n om m ax

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